Huawei proposes Tau Scaling Law and LogicFolding to circumvent lithography restrictions (heise.de)

• Huawei proposes Tau Scaling Law, shifting focus from transistor count to signal latency.
• LogicFolding stacks logic chips to shorten signal paths and reduce power.
• Huawei targets 1.4nm-equivalent density by 2031; first stacked Kirin chip in fall 2026.

"At ISCAS in Shanghai, Huawei's HiSilicon chief He Tingbo introduced the Tau Scaling Law to replace Moore's Law, focusing on signal latency rather than transistor density. LogicFolding stacks logic chips to shorten signal paths, reducing power. Huawei aims to catch up with leading foundries by 2031, targeting 1.4nm-equivalent density. A stacked Kirin processor is planned for autumn 2026. The move is driven by US sanctions blocking access to advanced ASML lithography tools."